This invention relates to a method of checking a memory, and more particularly to a method of checking a memory such as a read-only memory (ROM) or a memory for both read and write operations which is used primarily for reading only.
It is general practice, in systems that require high reliability to perform a check of read-out information, as by a parity check procedure, in order to prevent the erroneous system operation which can occur if false information is read out of a memory because of a malfunctioning memory element or some other problem. Generally the parity check method proceeds in the following manner. It should first be noted that a parity bit generating circuit and a parity check circuit are required, and that these are provided for in the computer processor. When data is written, the parity generating circuit forms a parity bit for each word which is to be stored in the memory, and causes the parity bit to be stored in the prescribed region of the memory. When the data is read out from the memory, the parity check circuit executes a parity check. Thus when data from the processor is written in the memory, the parity bit generating circuit forms a parity bit in accordance with odd or oven parity, and writes the parity bit in the prescribed region of the memory, which shares the same address as the data. Then, when the processor designates the address and the data is read out, the parity check circuit checks the data and issues an alarm if an error is detected. When this occurs the processor is interrupted by a well known method. In general, instruction words handled by a general micro-processor are composed of eight bits. This means that the number of bits which construct one word is increased to nine, since one bit must be added for the parity bit in the aforesaid parity check. On the other hand, in numerical control apparatus a read-only memory is used to store permanent data, such as a program for numerical control, and the read-only memory is almost always constructed of eight bits. That is to say, the read-only memory is composed of 8.times.n bits.
As is apparent from above-mentioned description, it is necessary to use the read-only memory (8.times.n bits) and a memory element constructed of 1.times.n bits, wherein the read-only memory is used for storing the instruction words and the memory element is used for storing the parity bits. However, there is no memory element constructed of 1.times.n bits available. For this reason, it is inevitable to substitute the read-only memory for the memory element (1.times.n bits), thereby substantially increasing the amount of hardware required.
It is also apparent that only 1/8 of the memory capacity is employed for the parity check, a fact which does not allow the memory to be used to the fullest possible extent. Moreover, in a comparatively small-scale system, the hardware for generating the parity bits and for checking them occupies a significant part of the overall hardware.